Cache design must meet many conflicting demands: high hit rates, low cost, low power, low latency and high throughput. We propose a novel cache design for 16-way associativity with cost and power consumption like 2-way associativity.

UNMET NEED
We propose a novel cache design with the following features:

• High effective cache capacity
• Misses are fast and cheap
• Fixed low Latency
• Low memory overhead
• Support of all cache operations
• Support cache coherency
• Multi-port extendable

OUR SOLUTION
Key technical elements of our cache design:

• 16-way associativity
• At most 2 tag comparisons per operation
• Single cache line read per hit
• 3 pipeline stages (<10 LL’s/stage)
• Issue rate: every clock cycle
• Obviate need for snoop filter
• Latency: 2-3 clock cycles

APPLICATIONS
• L2/L3/L4 caches in multi-core microprocessors
• Caches in network devices

INTELLECTUAL PROPERTY
Provisional patent application